View MAX15024AATB_4621689.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1053; Rev 2; 4/10
Single/Dual, 16ns, High Sink/Source Current Gate Drivers
General Description
The MAX15024/MAX15025 single/dual, high-speed MOSFET gate drivers are capable of operating at frequencies up to 1MHz with large capacitive loads. The MAX15024 includes internal source-and-sink output transistors with independent outputs allowing for control of the external MOSFET's rise and fall time. The MAX15024 is a single gate driver capable of sinking an 8A peak current and sourcing a 4A peak current. The MAX15025 is a dual gate driver capable of sinking a 4A peak current and sourcing a 2A peak current. An integrated adjustable LDO voltage regulator provides gatedrive amplitude control and optimization. The MAX15024A and MAX15025A/C accept transistorto-transistor (TTL) input logic levels while the MAX15024B and MAX15025B/D accept CMOS-input logic levels. High sourcing/sinking peak currents, a low propagation delay, and thermally enhanced packages make the MAX15024/MAX15025 ideal for high-frequency and high-power circuits. The MAX15024/ MAX15025 operate from a 4.5V to 28V supply. A separate output driver supply input enhances flexibility and permits a soft-start of the power MOSFETs used in synchronous rectifiers. The MAX15024/MAX15025 are available in 10-pin TDFN packages and are specified over the -40C to +125C automotive temperature range.
Features
o 8A Peak Sink Current/4A Peak Source Current (MAX15024) o 4A Peak Sink Current/2A Peak Source Current (MAX15025) o Low 16ns Propagation Delay o 4.5 V to 28V Supply Voltage Range o On-Board Adjustable LDO for Gate-Drive Amplitude Control and Optimization o Separate Output Driver Supply o Independent Source and Sink Outputs (MAX15024) o Matched Delays Between Inverting and Noninverting Inputs (MAX15024) o Matched Delays Between Channels (MAX15025) o CMOS or TTL Logic-Level Inputs with Hysteresis for Noise Immunity o -40C to +125C Operating Temperature Range o Thermal-Shutdown Protection o 1.95W Thermally Enhanced TDFN Power Packages
MAX15024/MAX15025
Applications
Synchronous Rectifier Drivers Power-Supply Modules Switching Power Supply
PART MAX15024AATB+T MAX15024BATB+T MAX15025AATB+T MAX15025BATB+T
N_OUT P_OUT PGND DRV REG
Ordering Information
PIN-PACKAGE 10 TDFN-EP** 10 TDFN-EP** 10 TDFN-EP** 10 TDFN-EP** 10 TDFN-EP** TOP MARK ATX ATY ATZ AUA AUB
Pin Configurations
TOP VIEW
MAX15025CATB+T
10
9
8
7
6
MAX15024
EP* 1 FB/SET 2 VCC 3 GND 4 IN+ 5 IN-
MAX15025DATB+T 10 TDFN-EP** AUC Note: All devices are specified over the -40C to +125C operating temperature range. +Denotes a lead-free package. **EP = Exposed pad. T = Tape and reel. See the Selector Guide at the end of the data sheet.
*EP = EXPOSED PAD.
TDFN
Pin Configurations continued at end of data sheet.
Block Diagrams appear at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
ABSOLUTE MAXIMUM RATINGS
VCC to GND ............................................................-0.3V to +30V REG to GND ..............-0.3V to the lower of +22V or (VCC + 0.3V) DRV to PGND .........................................................-0.3V to +22V IN_ ..........................................................................-0.3V to +22V FB/SET to GND.........................................................-0.3V to +6V P_OUT to DRV ........................................................-22V to +0.3V N_OUT to PGND.....................................................-0.3V to +22V OUT1, OUT2 to PGND ..............................-0.3V to (VDRV + 0.3V) PGND to GND .......................................................-0.3V to +0.3V P_OUT, N_OUT Continuous Source/Sink Current* .......... 200mA OUT1, OUT2 Continuous Source/Sink Current*................200mA Continuous Power Dissipation (TA = +70C) 10-Pin TDFN, Single-Layer Board (derate 18.5mW/C above +70C) ...........................1481.5mW Junction-to-Case Thermal Resistance (Note 1) ..............8.5C/W 10-Pin TDFN, Multilayer Board (derate 24.4mW/C above +70C) ...........................1951.2mW Junction-to-Case Thermal Resistance (Note 1) ..............8.5C/W Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C *Continuous output current is limited by the power dissipation of the package. Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal.tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MAX15024 ELECTRICAL CHARACTERISTICS
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = + 25C). (Note 2)
PARAMETER SYSTEM SPECIFICATIONS VCC powered only, VREG = VDRV decoupled with minimum 1F to GND MAX15024B MAX15024A 6.5 4.5 6.5 4.5 1.7 700 250 1.5 3.0 3.4 300 VCC rising VCC falling VREG VR_DO 12V < VCC < 28V, 0 < ILOAD < 10mA VCC = 6.5V, ILOAD = 100mA VCC = 4.5V, ILOAD = 50mA VCC = 12V, ILOAD = 0 to 100mA 12V < VCC < 28V External resistive divider connected at FB/SET VFB falling VFB = 4.5V (Note 3) -125 1.10 9 100 2 10 0.4 0.2 1 10 1.23 220 +125 1.35 11 0.9 V 0.5 % mV V mV nA 3.0 3.8 28.0 28.0 18.0 18.0 2.3 1350 V A A mA V mV s V SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Voltage Range
VCC
VCC = VREG = VDRV (MAX15024B) VCC = VREG = VDRV (MAX15024A) VDRV Turn-On Voltage Quiescent Supply Current Quiescent Supply Current Under UVLO Condition Switching Supply Current VCC Undervoltage Lockout VCC Undervoltage-Lockout Hysteresis VCC Undervoltage Lockout to Output Delay Output Voltage Dropout Voltage Load Regulation Line Regulation FB/SET Reference Voltage FB/SET Threshold FB/SET Input Leakage Current UVLO_ VCC VDRV_ON VCC = VREG = 10V, IN+ = VCC, IN- = GND IN_ = VCC or GND IN_ = VCC or GND Switching at 250kHz, CL = 0F VCC rising
REG REGULATOR (VCC = 12V, REG = VDRV, CL = 1F, FB/SET = GND) V
2
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = + 25C). (Note 2)
PARAMETER DRIVER OUTPUT (SINK) VCC = VREG = VDRV = 10V, sinking 100mA Driver Output Resistance RON-N TA = +25C TA = +125C 0.45 0.625 0.50 0.7 8 200 500 VCC = VREG = VDRV = 10V, sourcing 100mA Driver Output Resistance RON-P TA = +25C TA = +125C 0.875 1.2 0.95 1.25 4 500 MAX15024A MAX15024B MAX15024A MAX15024B MAX15024A MAX15024B VIN = 18V or VGND -75 0.4 1 0.01 10 +75 2.0 4.25 0.8 2 1.500 2.0 1.65 2.20 A mA 0.60 0.850 0.65 0.9 A nF mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX15024/MAX15025
VCC = VREG = VDRV = 4.5V, TA = +25C sinking 100mA TA = +125C (MAX15024A) VN_OUT = 10V SOA condition: CL x VDRV2 20J, for VDRV = 10V
Peak Output Current Maximum Load Capacitance Latchup Robustness DRIVER OUTPUT (SOURCE)
IPK-N
VCC = VREG = VDRV = 4.5V, TA = +25C sourcing 100mA TA = +125C (MAX15024A) VP_OUT = 0V
Peak Output Current Latchup Robustness LOGIC INPUTS Logic 1 Input Voltage Logic 0 Input Voltage Logic Input Hysteresis Logic Input Current Leakage Input Capacitance
IPK-P
VIH VIL
V V V A pF
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 10V, P_OUT AND N_OUT ARE CONNECTED TOGETHER (see Figure 1) CLOAD = 1nF Rise Time tR CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF Fall Time Turn-On Delay Time Turn-Off Delay Time Mismatch Propagation Delays from Inverting and Noninverting Inputs to Output tF tD-ON tD-OFF CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF (Note 3) CLOAD = 1nF (Note 3) CLOAD = 1nF (Note 3) 8 8 -9 3 12 24 3 8 16 16 16 1 32 32 +9 ns ns ns ns ns
_______________________________________________________________________________________
3
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = + 25C). (Note 2)
PARAMETER SYMBOL CLOAD = 1nF Rise Time tR CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF Fall Time Turn-On Delay Time Turn-Off Delay Time Mismatch Propagation Delays from Inverting and Noninverting Inputs to Output Minimum Input Pulse Width that Changes the Output THERMAL CHARACTERISTICS Thermal-Shutdown Temperature Thermal-Shutdown Temperature Hysteresis Temperature rising +160 15 C C tPW tF tD-ON tD-OFF CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF CLOAD = 1nF CLOAD = 1nF CONDITIONS MIN TYP 3 11 22 2.5 8 16 18 18 2 ns ns ns ns ns MAX UNITS
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 4.5V (see Figure 1) (MAX15024A)
15
ns
MAX15025 ELECTRICAL CHARACTERISTICS
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C). (Note 2)
PARAMETER SYSTEM SPECIFICATIONS VCC powered only, VREG = VDRV decoupled with minimum 1F to GND MAX15025B/D MAX15025A/C 6.5 4.5 1.7 700 250 1.5 3.0 3.4 3.0 3.8 6.5 4.5 28 28 18.0 18.0 2.3 1350 V A A mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Voltage Range
VCC
VCC = VREG = VDRV (MAX15025B/D) VCC = VREG = VDRV (MAX15025A/C) VDRV Turn-On Voltage Quiescent Supply Current Quiescent Supply Current Under UVLO Condition Switching Supply Current VCC Undervoltage Lockout UVLO_ VCC VDRV_ON VCC = VREG = 10V, IN1 = VCC, IN2 = VCC (MAX15025A/B) or GND for (MAX15025C/D) IN_ = VCC or GND IN_ = VCC or GND Switching at 250kHz, CL = 0F VCC rising
4
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C). (Note 2)
PARAMETER VCC Undervoltage-Lockout Hysteresis VCC Undervoltage Lockout to Output Delay Output Voltage Dropout Voltage Load Regulation Line Regulation FB/SET Reference Voltage FB/SET Threshold FB/SET Input Leakage Current DRIVER OUTPUT SINK VCC = VREG = VDRV = 10V, sinking 100mA Driver Output Resistance RON-N VCC = VREG = VDRV = 4.5V, sinking 100mA (MAX15025A/C) VOUT_ = 10V TA = +25C TA = +125C TA = +25C TA = +125C 1.0 1.25 1.10 1.5 4 100 500 VCC = VREG = VDRV = 10V, sourcing 100mA Driver Output Resistance RON-P VCC = VREG = VDRV = 4.5V, sourcing 100mA (MAX15025A/C) VOUT_ = 0V TA = +25C TA = +125C TA = +25C TA = +125C 1.75 2.25 1.85 2.50 2 500 MAX15025A/C MAX15025B/D MAX15025A/C MAX15025B/D MAX15025A/C MAX15025B/D VIN = 18V or VGND -75 0.4 1 +0.01 10 +75 2.0 4.25 0.8 2 2.50 3.50 2.60 3.75 A mA 1.6 2.10 1.65 2.2 A nF mA VREG VR_DO VCC rising VCC falling 12V < VCC < 28V, 0 < ILOAD < 10mA VCC = 6.5V, ILOAD = 100mA VCC = 4.5V, ILOAD = 50mA VCC = 12V, ILOAD = 0 to 100mA 12V < VCC < 28V External resistive divider connected at FB/SET VFB rising VFB = 4.5V -125 1.10 9 SYMBOL CONDITIONS MIN TYP 300 100 2 10 0.4 0.2 1 10 1.23 220 +125 1.35 11 0.9 0.5 MAX UNITS mV s
MAX15024/MAX15025
REG REGULATOR (VCC = 12V, VREG = VDRV, CL = 1F, FB/SET = GND) V V % mV V mV nA
Peak Output Current Maximum Load Capacitance Latchup Robustness DRIVER OUTPUT SOURCE
IPK-N
SOA condition: CL x VDRV2 20J, for VDRV = 10V
Peak Output Current Latchup Robustness LOGIC INPUTS Logic 1 Input Voltage Logic 0 Input Voltage Logic Input Hysteresis Logic Input Current Leakage Input Capacitance
IPK-P
VIH VIL
V V V A pF
_______________________________________________________________________________________
5
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C). (Note 2)
PARAMETER SYMBOL CLOAD = 1nF Rise Time tR CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF Fall Time Turn-On Delay Time Turn-Off Delay Time Mismatch Propagation Delays Between 2 Channels tF tD-ON tD-OFF CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF (Note 3) CLOAD = 1nF (Note 3) CLOAD = 1nF (Note 3) 8 8 -9 CONDITIONS MIN TYP 6 24 48 5 16 32 16 16 1 32 32 +9 ns ns ns ns ns MAX UNITS SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 10V (see Figure 1)
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 4.5V (see Figure 1) (MAX15025A/C) CLOAD = 1nF Rise Time tR CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF Fall Time Turn-On Delay Time Turn-Off Delay Time Mismatch Propagation Delays Between 2 Channels Minimum Input Pulse Width that Changes the Output THERMAL CHARACTERISTICS Thermal-Shutdown Temperature Thermal-Shutdown Temperature Hysteresis Temperature rising +160 15 C C tPW tF tD-ON tD-OFF CLOAD = 5nF CLOAD = 10nF CLOAD = 1nF CLOAD = 1nF CLOAD = 1nF 5 20 42 4 15 30 18 18 2 15 ns ns ns ns ns ns
Note 2: All devices are 100% production tested at TA = +25C. Limits over temperature are guaranteed by design. Note 3: Design guaranteed by bench characterization. Limits are not production tested.
6
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX15024/MAX15025
RISE TIME vs. SUPPLY VOLTAGE (DUAL DRIVER WITH 5nF LOAD)
MAX15024/25 toc01
FALL TIME vs. SUPPLY VOLTAGE (WITH 5nF LOAD)
MAX15024/25 toc02
PROPAGATION DELAY TIME vs. TEMPERATURE (1nF LOAD)
MAX15024/25 toc03
40 TA = +125C 30 RISE TIME (ns) TA = +85C 20 TA = 0C 10 TA = -40C TA = +25C MAX15025
30 MAX15025 25 FALL TIME (ns) TA = +125C TA = +85C 20
18 PROPAGATION DELAY TIME (ns) 16 14 12 FALLING 10 8 6
RISING
15
TA = 0C TA = -40C
TA = +25C
0 10 11 12 13 14 15 16 17 18 19 20 SUPPLY VOLTAGE (V)
10 10 12 14 16 18 20 SUPPLY VOLTAGE (V)
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (PROGRAMMED EXTERNALLY TO 5V)
MAX15024/25 toc04
SUPPLY CURRENT vs. LOAD CAPACITANCE
MAX15024/25 toc05
SUPPLY CURRENT vs. TEMPERATURE
1600 SUPPLY CURRENT (A) 1400 1200 1000 800 600 400 200 NOT SWITCHING SWITCHING 250kHz VCC = VREG = VDRV = 10V
MAX15024/25 toc06
2500 1MHz 2000 SUPPLY CURRENT (A) 500kHz
30 VCC = VREG = VDRV = 10V 24 SUPPLY CURRENT (mA) SWITCHING 250kHz
1800
1500 100kHz 1000 75kHz
18
12 NOT SWITCHING
500
40kHz
6
0 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V)
0 0 2000 4000 6000 8000 10,000 LOAD CAPACITANCE (nF)
0 -40 0 40 TEMPERATURE (C) 80 120
INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE (TTL)
MAX15024/25 toc07
SUPPLY CURRENT vs. LOGIC IN
MAX15024/25 toc08
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE (5nF RISING)
MAX15024/25 toc09
3.0 INPUT THRESHOLD VOLTAGE (V) 2.5 RISING 2.0 1.5 1.0 FALLING 0.5 0 4 8 12 SUPPLY VOLTAGE (V) 16
1600 1400 SUPPLY CURRENT (A) 1200 1000 800 600 400 200 00 INPUT HIGH TO LOW INPUT LOW TO HIGH
MAX15025 IN_ 1V/div
OUT_ 5V/div
20
0
1
2
3
4
5
6
20ns/div
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE (5nF FALLING)
MAX15024/25 toc10
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE (10nF RISING)
MAX15024/25 toc11
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE (10nF FALLING)
MAX15024/25 toc12
MAX15025
MAX15025 IN_ 1V/div
MAX15025
IN_ 1V/div
IN_ 1V/div
OUT_ 5V/div OUT_ 5V/div 20ns/div 20ns/div 20ns/div
OUT_ 5V/div
PROPAGATION DELAY MISMATCH vs. TEMPERATURE
PROPAGATION DELAY BETWEEN CHANNELS (ns)
MAX15024/25 toc13
LINE REGULATION OF VREG (PROGRAMMED EXTERNALLY TO 5.04V)
MAX15024/25 toc14
LOAD REGULATION OF VREG
MAX15024/25 toc15
3.0 2.5 2.0
5.3 5.2 5.1 VREG (V)
11.0
10.5 VREG (V)
1.5 1.0 0.5 0 -40 0 40 TEMPERATURE (C) 80 120
5.0 4.9
10.0
9.5 4.8 4.7 5 10 15 20 25 30 SUPPLY VOLTAGE 9.0 0 20 40 60 80 100 120 140 160 180 200 LOAD CURRENT (mA)
FB/SET VOLTAGE vs. TEMPERATURE
MAX15024/25 toc16
FB/SET CURRENT vs. TEMPERATURE
MAX15024/25 toc17
1.240
20
1.238 FB/SET VOLTAGE (V)
1.236
FB/SET CURRENT (nA)
15
10
1.234
5 1.232
1.230 0 20 40 60 80 100 120 TEMPERATURE (C)
0 0 20 40 60 80 100 120 TEMPERATURE (C)
8
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Pin Description
PIN MAX15024 MAX15025A MAX15025B 1 MAX15025C MAX15025D 1 NAME FUNCTION
1
FB/SET
LDO Regulator Output Set. Feedback for VREG adjustment (VFB > 200mV). Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a resistor ladder to set VREG. Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of 1F. Input of the internal housekeeping regulator and of the main REG regulator. Signal Ground Driver Noninverting Logic Input. Connect to VCC when not used. Driver 1 Noninverting Logic Input Driver Inverting Logic Input. Connect to GND when not used. Driver 2 Noninverting Logic Input Driver 2 Inverting Logic Input Power Ground. Sink current return. Source of the internal pulldown n-channel transistor. Sink Output. Open-drain n-channel output. N_OUT sinks current for power MOSFET turn-off. Driver 2 Output Source Output. Pullup p-channel output (open drain). Sources current for power MOSFET turn-on. Driver 1 Output Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1F ceramic capacitor to PGND placed in close proximity to the device. DRV can be powered independently from REG. Connect DRV, REG, and VCC together when there is no need for special DRV supply sequencing and the power-MOSFET gate voltage does not need to be regulated or limited. Voltage Regulator Output. Connect to DRV for driving the power MOSFET with regulated VGS amplitude. Bypass with a low-ESR 1F (minimum) ceramic capacitor to GND placed in close proximity to the device to ensure regulator stability. Exposed Pad. Internally connected to GND. Connect to GND plane or thermal pad and use multiple vias to a solid copper area on the bottom of the PCB.
2 3 4 -- 5 -- -- 6 7 -- 8 --
2 3 -- 4 -- 5 -- 6 -- 7 -- 8
2 3 -- 4 -- -- 5 6 -- 7 -- 8
VCC GND IN+ IN1 ININ2 IN2 PGND N_OUT OUT2 P_OUT OUT1
9
9
9
DRV
10
10
10
REG
--
--
--
EP
_______________________________________________________________________________________
9
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Detailed Description
The MAX15024 single gate driver's internal source and sink transistor outputs are brought out of the IC to independent outputs allowing control of the external MOSFET's rise and fall time. The MAX15024 single gate driver is capable of sinking an 8A peak current and sourcing a 4A peak current. The MAX15025 dual gate drivers are capable of sinking a 4A peak current and sourcing a 2A peak current. An integrated adjustable low-dropout linear voltage regulator (LDO) provides gate drive amplitude control and optimization. The single gate-driver propagation delay time is minimized and matched between the inverting and noninverting inputs. The dual gate-driver propagation delay is matched between channels. The MAX15024 has a dual input (IN+ and IN-), allows the use of an inverting or noninverting input, and is offered in TTL or CMOS-logic standards. The MAX15025 is offered with configurations of inverting and noninverting inputs with TTL or CMOS standards (see the Selector Guide).
Input Control
The MAX15024 features inverting and noninverting input terminals. These inputs provide for flexibility of design and use. Connect IN+ to VCC when using IN- as an inverting input. Connect IN- to GND when using IN+ as a noninverting input.
Shoot-Through Protection
The MAX15024/MAX15025 provide protection that avoids any cross-conduction between the internal pchannel and n-channel devices. It also eliminates shootthrough, thus reducing the quiescent supply current.
Exposed Pad (EP)
The MAX15024/MAX15025 include an exposed pad allowing greater heat dissipation from the internal die to the outside environment. Solder the exposed pad carefully to GND or thermal pad to enhance the thermal performance.
Applications Information
Supply Bypassing, Device Grounding, and Placement
Ample supply bypassing and device grounding are extremely important because when large external capacitive loads are driven, the peak current at the VDRV pin can approach 4A, while at the PGND pin, the peak current can approach 8A. V DRV drops and ground shifts are forms of negative feedback for inverters and, if excessive, can cause multiple switching when the inverting input is used and the input slew rate is low. The device driving the input should be referenced to the MAX15024/MAX15025 GND. Ground shifts due to insufficient device grounding can disturb other circuits sharing the same AC ground return path. Any series inductance in the VDRV, OUT_, and/or PGND paths can cause oscillations due to the very high di/dt that results when the MAX15024/MAX15025 are switched with any capacitive load. A 0.1F or larger value ceramic capacitor is recommended for bypassing VDRV to GND and should be placed as close to the pins as possible. When driving very large loads (> 10nF) at minimum rise time, 10F or more of parallel storage capacitance is recommended. A ground plane is highly recommended to minimize ground return resistance and series inductance. Care should be taken to place the MAX15024/MAX15025 as close as possible to the external MOSFET being driven to further minimize board inductance and AC path resistance.
LDO Voltage Regulator Feedback Control
The MAX15024/MAX15025 include an internal LDO designed to deliver a stable reference voltage for use as a supply voltage for the internal MOSFET gate drivers. Connect the LDO feedback FB/SET to GND to set VREG to a stable 10V. Connect FB/SET to a resistordivider between VREG and GND to set VREG: VREG = VFB/SET x (1 + R2 / R1) (see Figure 2)
VCC Undervoltage Lockout When VCC is below the UVLO threshold, the internal nchannel transistor is ON and the internal p-channel transistor is OFF, holding the output at GND independent of the state of the inputs so that the external MOSFETs remain OFF in the UVLO condition. The UVLO threshold is 3.5V (typ) with 200mV (typ) hysteresis to avoid chattering.
When the device is operated at very low temperatures and below the UVLO threshold, the driver output could go high impedance. In this case, it is recommended adding a 10k resistor to PGND to discharge the gate of the external MOSFET (see Figures 4 and 5).
10
______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers
Power Dissipation
Power dissipation of the MAX15024/MAX15025 consists of three components: the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). The sum of these components must be kept below the maximum power-dissipation limit. The quiescent current is 700A typ. The current required to charge and discharge the internal nodes is frequency dependent (see the Typical Operating Characteristics). The MAX15024/MAX15025 power dissipation when driving a ground-referenced resistive load is: P = D x RON(MAX) x ILOAD2 where D is the fraction of the period the MAX15024/ MAX15025s' output pulls high, RON(MAX) is the maximum on-resistance of the device with the output high (p-channel), and ILOAD is the output load current of the MAX15024/MAX15025. For capacitive loads, the power dissipation for each driver is: P = CLOAD x VDRV2 x FREQ where CLOAD is the capacitive load, VDRV is the driver supply voltage, and FREQ is the switching frequency. printed-circuit board (PCB) layout guidelines are recommended when designing with the MAX15024/MAX15025: * Place one or more 1F decoupling ceramic capacitor(s) from VDRV to PGND as close to the device as possible. At least one storage capacitor of 10F (min) should be located on the PCB with a low resistance path to the VCC pin of the MAX15024/MAX15025. * There are two AC current loops formed between the device and the gate of the MOSFET being driven. The MOSFET looks like a large capacitance from gate to source when the gate is being pulled low. The active current loop is from MOSFET gate to OUT_ of the MAX15024/MAX15025 to PGND of the MAX15024/MAX15025, and to the source of the MOSFET. When the gate of the MOSFET is being pulled high, the active current loop is from the VDD terminal of the VDRV terminal of decoupling capacitor, to the VDRV of the MAX15024/MAX15025, to the OUT_ of the MAX15024/MAX15025, to the MOSFET gate, to the MOSFET source, and to the negative terminal of the decoupling capacitor. Both charging current loop and discharging current loop are important. It is important to minimize the physical distance and the impedance in these AC current paths. * Keep the device as close as possible to the MOSFET. * In the multilayer PCB, the inner layers should consist of a GND plane containing the discharging and charging current loops.
MAX15024/MAX15025
Layout Information
The MAX15024/MAX15025 MOSFET drivers source and sink large currents to create very fast rise and fall edges at the gate of the switching MOSFET. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following
IN+ VIH VIL P_OUT AND N_OUT CONNECTED TOGETHER OR OUT1/OUT2
90%
10% tD-OFF tF tD-ON tR
Figure 1. Timing Diagram
______________________________________________________________________________________
11
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Typical Operating Circuits
REG DRV R2 FB/SET R1 N_OUT VCC (UP TO 28V) VCC GND ININ+ PGND
VCC (UP TO 18V) VCC DRV
VDRV < 18V
MAX15024
REG P_OUT FB/SET
C1
MAX15024
P_OUT
GND
N_OUT
ININ+
PGND
Figure 2. Use R1, R2 to program VREG < 18V, OR. Connect FB/SET to GND for VREG = 10V (Connect EP to GND)
Figure 3. Operation Using a Different Supply Rail for DRV (Connect EP to GND)
VCC (UP TO 18V) VCC REG DRV R2
REG DRV
MAX15025
OUT1 FB/SET
MAX15024
R1 FB/SET P_OUT VCC (UP TO 28V) GND N_OUT
OUT2 VCC GND PGND
INPGND IN+
IN1 IN2
Figure 4. Operation Using a VCC = DRV = REG (Connect EP to GND)
Figure 5. Use R1, R2 to program VREG < 18V, OR. Connect FB/SET to GND for VREG = 10V (Connect EP to GND)
12
______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers
Block Diagrams
MAX15024/MAX15025
VCC LDO UVLO FB/SET
REG
DRV IN_ LOGIC LEVEL SHIFT-UP IN+ PREDRIVER P P_OUT N_OUT IN_ LOGIC LEVEL SHIFT-UP PREDRIVER N PGND
IN-
GND
MAX15024A MAX15024B
VCC LDO UVLO FB/SET
REG
DRV
IN_ LOGIC LEVEL SHIFT-UP IN1 IN_ LOGIC LEVEL SHIFT-UP IN_ LOGIC LEVEL SHIFT-UP IN2 GND IN_ LOGIC LEVEL SHIFT-UP
PREDRIVER
P OUT1
PREDRIVER PREDRIVER P
N
OUT2 PREDRIVER N PGND
MAX15025
______________________________________________________________________________________
13
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Selector Guide
PART MAX15024AATB+ MAX15024BATB+ MAX15025AATB+ MAX15025BATB+ MAX15025CATB+ MAX15025DATB+ NO. OF CHANNELS 1 1 2 2 2 2 PEAK CURRENTS (SINK/SOURCE) 8A/4A 8A/4A 4A/2A 4A/2A 4A/2A 4A/2A INPUTS Complementary Complementary Noninverting Noninverting Noninverting (1)/ Inverting (2) Noninverting (1)/ Inverting (2) LOGIC LEVELS TTL CMOS TTL CMOS TTL CMOS TOP MARK ATX ATY ATZ AUA AUB AUC
Note: All devices operate in a -40C to +125C temperature range and come in a 10-pin TDFN package.
Pin Configurations (continued)
TOP VIEW
PGND OUT1 OUT2 DRV REG PGND 6 5 IN2 OUT1 8 3 GND OUT2 7 4 IN1 DRV 9 EP 3 GND 4 IN1 5 IN2 1 FB/SET 2 VCC REG 10
10
9
8
7
6
MAX15025A MAX15025B
EP 1 FB/SET 2 VCC
MAX15025C MAX15025D
TDFN
TDFN
14
______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 10 TDFN PACKAGE CODE T1033-1 DOCUMENT NO. 21-0137
______________________________________________________________________________________
15
Single/Dual, 16ns, High Sink/Source Current Gate Drivers MAX15024/MAX15025
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 10/07 3/08 4/10 Initial release Released MAX15024A/MAX15025B/C/D versions Removed future product (MAX15024C/D, MAX15025E-H); minimum and maximum specifications added to the EC table DESCRIPTION PAGES CHANGED -- 1-6, 9, 13 1-6, 9, 10, 12-15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX15024AATB

	To Download MAX15024AATB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .